The 8th International Forum on
Semiconductor Technology

19 - 21 June 2005, The Pan Pacific Hotel Yokohama, Japan

As semiconductor technology has advanced, it has become increasingly difficult to continue scaling the speed of integrated circuits. The 8th International Forum on Semiconductor Technology (IFST 2005), June 19-21, 2005, will focus on addressing this challenge and others facing the global semiconductor industry. IFST 2005 is designed to bring together engineers and scientists from around the world to discuss advances in semiconductor technology and enhance global cooperation in semiconductor research and development.

IFST 2005 is supported by global and regional semiconductor consortia and industry organizations and is co-sponsored by ASET, SEAJ, Selete, SEMI, SIRIJ and STARC.

Agenda

Sunday, June 19 18:00-19:00 Welcome Cocktail Reception Monday, June 20 10:00-10:10 Welcome and Opening Remarks Masataka Hirose, MIRAI Session 1 Design Challenges for Manufacturing chaired by Katsuhiro Shimohigashi, STARC and Dinesh Mehta, SRC 10:10-10:50 Introductory Design Talk Overview of SoC and SiP Technology for Digital Consumer Electronics Akira Matsuzawa, Tokyo Institute of Technology 10:50-11:15 Bridging the Gaps between System Level Complexity and Nano-scale Uncertainties Hugo De Man, IMEC 11:15-11:40 Design Methodologies Toward DFM Nobuyuki Nishiguchi, STARC 11:40-12:05 Design for Manufacturing: An SRCPerspective Ralph K. Cavin, III, SRC 12:05-13:35 Lunch 13:35-14:00 Design of Robust IP for Yieldand Time to Market Paul Simon, Philips Semiconductors 14:00-14:25 Patterning Friendly Design Methdology for 65-nm and Beyond Technology Nodes Soichi Inoue, Toshiba 14:25-14:50 A Shared Information Framework across Design and Manufacturing; Opportunities, Objectives and Obstacles Donald R. Cottrell, Si2 14:50-15:10 Break Session 2:Next Generation Lithography (NGL) chaired by Akihiko Morino, Selete 15:10-15:50 Introductory Technology Talk Lithography Roadmap: from ArF Immersion to EUVL NO.1 NO.2 Luc Van den hove, IMEC 15:50-17:20 Panel Discussion EUV versus Optical with RET for 45nm and beyond: from Technology to Economics/Cost Perspective Moderators : Shinji Okazaki, ASET Giang Dao, SEMATECH Panelists : William H. Arnold, ASML Naoya Hayashi, Dai Nippon Printing Naomichi Abe, EUVA Michael Lercel, IBM Luc Van den hove, IMEC Scott Hector, SEMATECH 17:30-19:30 Dinner Tuesday, June 21 Session 3: Panel Discussion 9:30-11:00 Devices and Technologies for hp32 and beyond Moderators : Toshiro Hiramoto, University of Tokyo James A. Hutchby, SRC Panelists Meikei Ieong, IBM Simon Deleonibus, LETI Judy L. Hoyt, MIT Makoto Yoshimi, SOITEC Asia Kazunari Ishimaru, Toshiba Summary Hiramoto 11:00-11:15 Break Session 4: Emerging Research Technologies (from materials to devices) chaired by Michel Brillouet, Leti 11:15-11:40 Highly Miniaturized System for Biology and Health Clerc Jean Frederic, CEA 11:40-12:05 The Search for Alternative Logic Devices Beyond CMOS George Bourianoff, Intel 12:05-12:30 Overview of Future Memory Devices - from Stacked Memory, Gain Memory, SEM to Molecular Memory Kazuo Nakazato, Nagoya University 12:30-12:35 IFST2006 Michael Polcari, SEMATECH 12:35-12:45 Closing Remarks Kazuo Miyazawa, ASET

IFST 2005 Committee Member

<IFST 2005 Executive Committee>

Masataka Hirose - MIRAI (Chair)

Toshiaki Masuhara - MIRAI (Vice Chair)

Akihiko Morino - Selete

Dennosuke Uchida - SEMI Japan

Dinesh Mehta - SRC

Gilbert Declerck - IMEC

Hiromi Sakurai - Selete

Katsuhiro Shimohigashi - STARC

Kazuo Miyazawa - ASET

Kenji Maeguchi - SIRIJ

Masanori Kikuchi - SEAJ

Michel Brillouet - CEA/LETI

Michael Polcari - ISMT

Peter Tischer - MEDEA+

<IFST 2005 Program Committee>

Seiichiro Kawamura - MIRAI (Chair)

Masao Kanazawa - ASET

Eijiro Toyoda - STARC

Betsy Weitzman - ISMT

Dieter Gotz - MEDEA+

<IFST 2005 Steering Committee>

Masao Kanazawa - ASET(Chair)

Seiichiro Kawamura - MIRAI

Eijiro Toyoda - STARC

SEMI Japan

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